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Ladder Logic Tool
The application is this example reads and parses
Microlok and Genisys processor program files with Boolean logic and converts
this to a graphical user interface for reading and creating processor logic in a
more user friendly environment.
The application in this example is MDI (multiple
document interface) whereby multiple program file can be edited simultaneously.
Drag
and drop functions allow settings to be dragged from one
application to another. |
Ladder Tool with two MICROLOK
source files open
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When multiple Application Source Files are open within
the main window, either clicking on the desired document window directly, or by
selecting the Tab containing the Application Source File name beneath the Main
menu, can select individual Application Source Files for viewing or editing. All
document windows can be moved or sized by selecting the document window with the
mouse and dragging or stretching, however, these individual windows cannot be
moved or sized beyond the viewable area of the main screen of the Ladder
Development Tool. If there is not sufficient viewing area available to view the
entire window of an Application Source File, it may be necessary to either
increase the size of the main screen, or to reduce the size of the Application
Source File window. The Window menu on the main application window allows
for center, cascade, tile, maximize, or normal of a document window within the
Ladder Development Tool as needed.
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Ladder Diagrams
In the Ladder Development Tool, a
Ladder Logic Diagram is a visual representation of all Boolean ASSIGN statements
residing within an Application Source File.
Each ASSIGN statement is converted
into an individual rung, which is a logic structure that allows one or more
combinations of inputs and outputs to set the value of one or more outputs. All
inputs and outputs can be either physical or logical I/O.
A Rung consists of
elements that represent I/O points, constants, or internally defined variables.
The Ladder
Development Tool reads Boolean expressions from an Application Source File and
converts them to a graphical representation of the logic represented by the
expression. |
Boolean to Ladder Conversion
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View of Boolean converted to
Ladder Logic in the application
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The grouping symbols and OR conditions found within a Boolean
expression can be translated directly to ladder logic branching.
Once
imported into the application, the user can insert or
append new rungs, copy paste rungs, modify rungs, or
remove rungs as required.
Individual elments, such as contacts and breakers can be
inserted anyway rules apply, and the ladder rungs can
easily be viewed as Boolean expressions at any time by
right clicking on a rung and selecting the appropriate
menu selection item. |
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The Ladder Logic Development Tool
displays a window for all defined Links and Stations. The detail window allows
modification of each particular Link or Station. New Links and Stations can be
added, removed, cut, copied, and pasted. The properties of each can be modified
as needed.
GENISYS II supports
GENISYS and DAB protocol serial communication Links. Up to 6 serial
communication Links may be defined. Up to 4 serial communication Links may be
simultaneously enabled. The COMM declaration heads the serial communication
section of the GENISYS II application program.
This
illustration shows an example of adding a specific Link to the Application
Source File via the Ladder Tool application interface. |
Defining Links
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A Board is an
input/output (I/O) card. Every card definition has a Board keyword, a Type
specification, an Enable flag, and a Board-specific definition.
The card cage imposes a
physical limit of 16 I/O cards. The application can define at most 32 I/O
Boards. No more than 16 I/O cards can be enabled in a single configuration.
Different types of I/O cards are placed in different address spaces, or address
classes. The compiler assigns addresses by class in the order of definition of
the Board.
I/O Boards are specified
in the user's application logic program. For every I/O Board defined, both the
Ladder Development Tool and the compiler create bits based on the Board's name.
Unlike industrial
programmable controllers, MICROLOK II and GENISYS II have no fixed mapping
between the physical locations of I/O boards in the card file and their address,
or the way they are referenced from within the Application Program. The
Application Compiler, based on the order in which the boards are defined within
the Application Source File, determines addresses for the I/O boards.
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The Generic System
software reports errors with I/O boards based on the position of their
definition within the Application Source File. Thus, the Ladder Logic
Development Tool shows the mapping as the definition order and not the physical
location of boards within the card file.The physical location of
boards in the I/O card file cannot be edited separately from their logical order
in the Ladder Development Tool.
The ordering of bits on an I/O board can be
rearranged. The logical order of Boards and bits can be changed using drag and
drop methods.
This
illustration shows an example of adding a specific Board to the Application
Source File. |
Defining Boards
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Defining Board Variables
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Variables must be assigned to Board inputs and outputs so the coding logic
within the Application Source File can access these I/O points. Board I/O
variables must be added in the Board I/O window.
This
illustration shows an example of adding Board Variables to a specific Board to the Application
Source File.
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